1. Field of the Invention
The present invention relates to a semiconductor device including a MOS transistor to which high driving performance is required, and relates to a method of manufacturing the semiconductor device.
2. Description of the Related Art
A MOS transistor is a core electronic element in electronics. It is important to achieve miniaturization of the MOS transistor and high driving performance thereof. One of methods of imparting high driving performance to the MOS transistor is expansion of a gate width to reduce ON resistance. However, there is a problem that a large gate width needs a wide occupation area for the MOS transistor. As a solution thereto, there is proposed a technology by which a large gate width is given while suppressing increase of the occupation area of the MOS transistor. (For example, see JP 2006-49826 A)
Hereinafter, a conventional semiconductor device will be described with reference to FIGS. 4A to 4D. As shown in a perspective view of FIG. 4A, the conventional semiconductor device includes a trench portion 8 provided in a well 17 and a gate electrode 10 provided in the trench portion 8 and on the top surface thereof on a gate insulating film 9. In a surface portion of the well 17, one side of the gate electrode 10 is provided with a source region 12 and the other side thereof is provided with a drain region 13. FIG. 4B is a sectional view of a planar portion taken along a cut surface A-A of FIG. 4A, and FIG. 4C is a sectional view taken along a cut surface B-B of FIG. 4A. As shown in FIG. 4C, since the gate electrode 10 is provided in the trench portion 8, a total length of the curve extending in the B-B direction of the gate electrode 10 brought into contact with the gate insulating film 9 gives a gate width.
As described above, since the gate portion has the trench structure including a convex portion and a concave portion, the actual gate width can be larger than the width of the gate electrode simply made on a flat surface thereof. Accordingly, the ON resistance per unit area can be reduced without lowering the withstanding voltage of the MOS transistor.
The inventor of the present invention has found a problem that in the structure of the semiconductor device described above, an actual driving performance can not reach the expected driving performance. It has also been found that the driving performance varies depending on the gate length and tends to be low in a short gate length device.
It is presumed that this phenomenon is caused by non-uniform current flow in the channel generated between the source and the drain: most current flows along path A which is a planar portion where the trench portion 8 is not formed; a little current flows along path B which is a side surface of the trench portion 8, which is parallel to the channel in the direction connecting the source and the drain, and along path C which is a bottom surface of the trench portion 8, as shown in FIG. 4D. Accordingly, the current tends to concentrate to the path A in the short gate length device, which is conceived to be a cause of the driving performance lowering in the short gate length device.